Implementation of an FPGA-Based Current Control and SVPWM ASIC with Asymmetric Five-Segment Switching Scheme for AC Motor Drives

This paper presents the design and implementation of an application-specific integrated circuit (ASIC) for a discrete-time current control space-vector pulse-width modulation (SVPWM) with asymmetric five-segment switching scheme AC motor drives. As compared to conventional three-phase symmetric seven-segment SVPWM scheme, proposed method involves two-phase in each period, so inverter times power loss can be reduced by 33%. In addition, produced PWM signal is respect center-symmetric triangular carrier wave, voltage command from output given half period time interval, hence increasing system bandwidth allowing drive better dynamic response. For verification function stationary reference frame also included ASIC. The firstly verified using PSIM simulation tool. Then, DE0-nano field programmable gate array (FPGA) board employed 300W permanent-magnet synchronous (PMSM) experimental